This invention relates to a method of inspecting a semiconductor non-volatile memory device, and more particularly a method of inspecting memorized data retention characteristics of non-volatile memory element including a plurality of field effect transistors having a floating gate.
The construction and operation of a typical non-volatile MOS memory device will first be described. The memory device comprises a non-volatile semiconductor memory element in which a plurality of non-volatile semiconductor transistors such as FAMOS (Floating-gate Avalanche-injection Metal Oxide Semiconductor) transistors are provided as memory cells.
FIG. 1 is a cross-sectional view showing a FAMOS transistor. The transistor is one type of the semi-conductor non-volatile memory cells. The transistor shown in FIG. 1 comprises a semiconductor substrate 1 of one conductive type, a terminal 2 in contact with a substrate electrode 1a provided on the back surface of the semiconductor substrate 1, source and drain regions 3 and 4 of the opposite conductivity type formed separately in one major surface of the substrate by introducing an impurity into the substrate 1, metal conductors 5 and 6 in ohmic contact with the source and drain regions 3 and 4, respectively, source and drain terminals 7 and 8 respectively connected to the metal conductors 5 and 6, a floating gate 9 formed on a gate oxide film 13a and surrounded completely by an oxide film 13b so that the floating gate 9 maintains perfectly an electrically floating state, a control gate 10 provided on the oxide film 13b above the floating gate 9, a metal conductor 11 in ohmic contact with the control gate 10, and a control gate terminal 12 connected to the metal conductor 11.
In the above-described FAMOS transistor, the current flowing between the source and drain regions 3 and 4 is controlled by a voltage applied to the control gate terminal 12 and the potential of the floating gate 9. The potential of the floating gate 9 is determined by the electric charge stored therein. Since the floating gate 9 is completely surrounded by an insulating material such as silicon dioxide, the electric charge in the floating gate 9 remains even when an external power source is interrupted. Ideally, the electric charge stored in the floating gate would be retained eternally. As a consequence, the transistors are provided in the memory element or memory chip of the non-volatile memory device. And the transistor is employed as a non-volatile memory cell by making presence and absence of the electric charge stored in the floating gate correspond to binary values "1" and "0", respectively.
An actually used semiconductor non-volatile memory device is incorporated with about several thousands to several tens of thousands of the memory transistors described above in the memory element and in individual memory transistors shown in FIG. 1, electric charges present in some of the floating gates, but not in the other floating gates. In such a non-volatile semiconductor device, the potential of the floating gate 9 does not vary under an ideal state as described previously, but for some reasons, an electric charge is injected into the floating gate or it flows out, thus varying the potential of the floating gate 9. When such variation is small, highly reliable data retention characteristics can be realized. In order to inspect improper data retention characteristics, that is, potential variation of floating gate, it takes a long time under an actual operating condition. Therefore, for inspecting memory devices having improper data retention characteristics, a special heat aging over a relatively long time is necessary, thus reducing the productivity.